1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of Related Art
In general, an LDMOSFET is known as a high withstand voltage device employed for a power MOSFET.
FIG. 10 is a schematic sectional view of a semiconductor device including a conventional LDMOSFET.
A semiconductor device 101 includes a thick-film SOI substrate 102. The thick-film SOI substrate 102 has a structure obtained by laminating an N−-type active layer 105 made of silicon on a silicon substrate 103 through a BOX layer 104 made of silicon oxide.
In the active layer 105, a deep trench 106 having a depth reaching the BOX layer 104 from the surface thereof is formed to pass through the active layer 105 in the thickness direction. The inner side surface of the deep trench 106 is covered with a silicon oxide film 107.
The inner side of the silicon oxide film 107 is filled up with polysilicon 108. Thus, an element forming region 109 surrounded by the deep trench 106 and dielectrically isolated from the periphery thereof by the BOX layer 104 and the silicon oxide film 107 is formed on the active layer 105.
An LDMOSFET 110 is formed in the element forming region 109. More specifically, a P-type body region 111 is formed in the active layer 105 in the element forming region 109. The body region 111 is formed along the side surface of the deep trench 106 over the entire thickness of the active layer 105.
The region of the element forming region 109 other than the body region 111 is an N−-type drift region 112.
On a surface layer portion of the body region 111, an N+-type source region 113 and a P+-type body contact region 114 are formed to be adjacent to each other on positions separated from the drift region 112. On a surface layer portion of the drift region 112, an N+-type drain region 115 is formed on a position separated from the body region 111.
On the surface of the drift region 112, a field oxide film 116 is formed on a portion between the drain region 115 and the body region 111 at an interval from the body region 111.
Between the source region 113 and the field oxide film 116, a gate oxide film 117 is formed on the surface of the active layer 105. A gate electrode plate 118 is formed on the gate oxide film 117. The gate electrode plate 118 is opposed to the body region 111 and the drift region 112 through the gate oxide film 117.
On the field oxide film 116, a field plate 119 integral with the gate electrode plate 118 is formed to extend onto the peripheral edge portion of the field oxide film 116.
Four first floating plates 120 are formed on the field oxide film 116. The four first floating plates 120 are in the form of rings, having a constant width, similar to one another. The four first floating plates 120 are arranged to form a quadruple ring surrounding a drain electrode plate 122 (described later) connected to the drain region 115 and to divide the space between the drain electrode plate 122 and the field plate 119 at regular intervals. The first floating plates 120 are opposed to the drift region 112 through the field oxide film 116.
A source electrode plate 121 extending over the source region 113 and the body contact region 114 is formed on the body region 111. The source electrode plate 121 is connected to the source region 113 and the body contact region 114.
The drain electrode plate 122 is formed on the drain region 115. The drain electrode plate 122 is connected to the drain region 115.
The upper portion of the thick-film SOI substrate 102 is covered with a first interlayer dielectric film 123 made of silicon oxide.
Five second floating plates 124 are formed on the first interlayer dielectric film 123. The second floating plates 124 are in the form of rings, having a constant width, similar to the first floating plates 120. The five second floating plates 124 are dividedly arranged one by one on a central portion between the drain electrode plate 122 and the first floating plate 120 adjacent thereto, central portions between the adjacent ones of the first floating plates 120, and a central portion between the field plate 119 and the first floating plate 120 adjacent thereto respectively. In other words, the five second floating plates 124 are arranged at regular intervals while the second floating plates 124 and the first floating plates 120 are alternately arranged in plan view between the drain electrode plate 122 and the field plate 119.
The upper portion of the first interlayer dielectric film 123 is covered with a second interlayer dielectric film 125 made of silicon oxide.
A source contact hole 12 6 facing the source electrode plate 121 is formed in the first interlayer dielectric film 123 and the second interlayer dielectric film 125 to pass through the same. Further, a drain contact hole 127 facing the drain electrode plate 122 is formed in the first interlayer dielectric film 123 and the second interlayer dielectric film 125 to pass through the same.
A source wire 128 and a drain wire 129 are formed on the second interlayer dielectric film 125. The source wire 128 is connected to the source electrode plate 121 through a source contact plug 130 embedded in the source contact hole 126. The drain wire 129 is connected to the drain electrode plate 122 through a drain contact plug 131 embedded in the drain contact hole 127.
A current can be fed between the source region 113 and the drain region 115 (between a source and a drain) through the drift region 112 by grounding the source wire 128 and controlling the potential of the gate electrode plate 118 while applying a positive-polarity voltage (a drain voltage) to the drain wire 129 thereby forming a channel in the vicinity of the interface between the body region 111 and the gate oxide film 117.